2Mx36 & 4Mx18 DDRII CIO b4 SRAM

K7I643684M

K7I641884M

- 9 -

Rev. 1.3 March 2007

Notes: 1. X means "Don

′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

↑).

3. Assumes a WRITE cycle was initiated.

4. This table illustrates operation for x18 devices.

K

K

OPERATION

↑

L

L

WRITE ALL BYTEs (K

↑ )

↑

L

L

WRITE ALL BYTEs (K

↑ )

↑

L

H

WRITE BYTE 0 (K

↑ )

↑

L

H

WRITE BYTE 0 (K

↑ )

↑

H

L

WRITE BYTE 1 (K

↑ )

↑

H

L

WRITE BYTE 1 (K

↑ )

↑

H

H

WRITE NOTHING (K

↑ )

↑

H

H

WRITE NOTHING (K

↑ )

Notes: 1. X means "Don

′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

↑ ).

3. Assumes a WRITE cycle was initiated.

K

K

OPERATION

↑

LLLL

WRITE ALL BYTEs (K

↑ )

↑

LLLL

WRITE ALL BYTEs (K

↑ )

↑

L

H

H

H

WRITE BYTE 0 (K

↑ )

↑

L

H

H

H

WRITE BYTE 0 (K

↑ )

↑

H

L

H

H

WRITE BYTE 1 (K

↑ )

↑

H

L

H

H

WRITE BYTE 1 (K

↑ )

↑

H

H

L

L

WRITE BYTE 2 and BYTE 3 (K

↑ )

↑

H

H

L

L

WRITE BYTE 2 and BYTE 3 (K

↑ )

↑

HHHH

WRITE NOTHING (K

↑ )

↑

HHHH

WRITE NOTHING (K

↑ )

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don

′t Care".

2. The rising edge of clock is symbolized by (

↑).

3. Before enter into clock stop status, all pending read and write operations will be completed.

K

LD

R/W

Q

OPERATION

Q(A0)

Q(A1)

Q(A2)

Q(A3)

Stopped

X

X

Previous

state

Previous

state

Previous

state

Previous

state

Clock Stop

↑

H

X

High-Z

High-Z

High-Z

High-Z

No Operation

↑

LH

C(t+1)

C(t+2)

C(t+2)

C(t+3)

Read

↑

L

L

Din at K(t+1) Din at K(t+1) Din at K(t+2) Din at K(t+2)

Write