K4S510732B

CMOS SDRAM

Rev. 0.0 Feb.2001

Preliminary

The K4S510732B is 536,870,912 bits synchronous high data rate

Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabri-

cated with SAMSUNG's high performance CMOS technology. Syn-

chronous design allows precise cycle control with the use of

system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system appli-

cations.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

16M x 8Bit x 4 Banks Synchronous DRAM

ORDERING INFORMATION

Part No.

Max Freq.

Interface

Package

K4S510732B-TC/L75

133MHz(CL=3)

LVTTL

54pin

TSOP(II)

K4S510732B-TC/L1H

100MHz(CL=2)

K4S510732B-TC/L1L

100MHz(CL=3)

32Mx8

32Mx8

A0~A12,BA0,BA1

DQ0 ~ DQ7

CLK,CAS,RAS

/WE,DQM

/CS1,CKE1

/CS0,CKE0

Staktek’s stacking technology is Samsung’s stacking technology of choice.