Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHB50N03T

Standard level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

standard level field-effect power

transistor in a plastic envelope

V

DS

Drain-source voltage

30

V

suitable for surface mounting using

I

D

Drain current (DC)

50

A

’trench’ technology. The device

P

tot

Total power dissipation

94

W

features very low on-state resistance

T

j

Junction temperature

175

˚C

and has integral zener diodes giving

R

DS(ON)

Drain-source on-state

21

m

Ω

ESD protection up to 2kV. It is

resistance

V

intended

for

use

in

DC-DC

converters and general purpose

switching applications.

PINNING - SOT404

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

mb

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

30

V

V

DGR

Drain-gate voltage

R

-30

V

±V

GS

Gate-source voltage

-

-

20

V

I

D

Drain current (DC)

T

-

50

A

I

D

Drain current (DC)

T

-

29

A

I

DM

Drain current (pulse peak value)

T

-

200

A

P

tot

Total power dissipation

T

-

94

W

T

Storage & operating temperature

-

- 55

175

˚C

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

-

1.6

K/W

mounting base

R

th j-a

Thermal resistance junction to

pcb mounted, minimum

50

-

K/W

ambient

footprint

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

C

Electrostatic discharge capacitor

Human body model

-

2

kV

voltage, all pins

(100 pF, 1.5 k

Ω)

d

g

s

13

mb

2

September 1997

1

Rev 1.100