Electronic Components Datasheet Search |
|
TL16C2752 Datasheet(PDF) 4 Page - Texas Instruments |
|
|
TL16C2752 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 25 page www.ti.com TL16C2752 Block Diagram Crystal OSC Buffer Data Bus Interface A2 − A0 D7 − D0 CS CHSEL IOR IOW INTA INTB TXRDYA TXRDYB MFA MFB RESET XTAL1 XTAL2 BAUD Rate Gen 64 Byte Tx FIFO 64 Byte Rx FIFO Tx IR ENC UART Channel A BAUD Rate Gen 64 Byte Tx FIFO 64 Byte Rx FIFO UART Channel B CTSA DTRA DSRA, RIA, CDA RTSA CTSB DTRB DSRB, RIB, CDB RTSB VCC GND TXA RXA TXB RXB UART Regs UART Regs Rx IR DEC Tx IR ENC Rx IR DEC DEVICE INFORMATION TL16C2752 SLWS188 – JUNE 2006 A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME FN NO. RHB NO. A0 10 3 I Address 0 select bit. Internal registers address selection A1 14 6 I Address 1 select bit. Internal registers address selection A2 15 7 I Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that CDA, CDB 42, 30 – I channel. The state of these inputs is reflected in the modem status register (MSR). These inputs should be pulled high if unused. Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate CHSEL 16 8 I function register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS is low. It is especially useful during the initialization routine. UART chip select (active low). This pin selects channel A or B in accordance with the state of CS 18 10 I the CHSEL pin. This allows data to be transferred between the user CPU and the 2552. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit CTSA, data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the 40, 28 25, 17 I CTSB transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. These inputs should be pulled high if unused. 4 Submit Documentation Feedback |
Similar Part No. - TL16C2752 |
|
Similar Description - TL16C2752 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |