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TMX320DM6443ZWT Datasheet(PDF) 1 Page - Texas Instruments |
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TMX320DM6443ZWT Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 221 page  www.ti.com 1 Digital Media System-on-Chip (DMSoC) 1.1 Features TMS320DM6443 Digital Media System-on-Chip SPRS282E – DECEMBER 2005 – REVISED MARCH 2007 • High-Performance Digital Media SoC • ARM926EJ-S Core – 594-MHz C64x+™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – 297-MHz ARM926EJ-S™ Clock Rate – DSP Instruction Extensions and Single – Eight 32-Bit C64x+ Instructions/Cycle Cycle MAC – 4752 C64x+ MIPS – ARM® Jazelle® Technology – Fully Software-Compatible With C64x / – EmbeddedICE-RT™ Logic for Real-Time ARM9™ Debug • Advanced Very-Long-Instruction-Word (VLIW) • ARM9 Memory Architecture TMS320C64x+™ DSP Core – 16K-Byte Instruction Cache – Eight Highly Independent Functional Units – 8K-Byte Data Cache • Six ALUs (32-/40-Bit), Each Supports – 16K-Byte RAM Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle – 8K-Byte ROM • Two Multipliers Support Four 16 x 16-Bit • Emulation Trace Buffer™ (ETB11™) With 4-KB Multiplies (32-Bit Results) per Clock Memory for ARM9 Debug Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Endianness: Little Endian for ARM and DSP Results) per Clock Cycle • Video Processing Subsystem – Load-Store Architecture With Non-Aligned – Resize Engine Provides: Support • Resize Images From 1/4x to 4x – 64 32-Bit General-Purpose Registers • Separate Horizontal and Vertical Control – Instruction Packing Reduces Code Size – Back End Provides: – All Instructions Conditional • Hardware On-Screen Display (OSD) – Additional C64x+™ Enhancements • 4 - 54 MHz DACs for a Combination of • Protected Mode Operation • Composite NTSC/PAL Video • Exceptions Support for Error Detection and Program Redirection • Luma/Chroma Separate Video (S-video) • Hardware Support for Modulo Loop Operation • Component (YPbPr or RGB) Video (Progressive) • C64x+ Instruction Set Features • Digital Output – Byte-Addressable (8-/16-/32-/64-Bit Data) • 8-/16-Bit YUV or up to 24-Bit RGB – 8-Bit Overflow Protection • HD Resolution – Bit-Field Extract, Set, Clear • Up to 2 Video Windows – Normalization, Saturation, Bit-Counting • External Memory Interfaces (EMIFs) – Compact 16-Bit Instructions – 32-Bit DDR2 SDRAM Memory Controller – Additional Instructions to Support Complex With 256M-Byte Address Space (1.8-V I/O) Multiplies – Asynchronous16-Bit Wide EMIF (EMIFA) • C64x+ L1/L2 Memory Architecture With 128M-Byte Address Reach – 32K-Byte L1P Program RAM/Cache (Direct • Flash Memory Interfaces Mapped) • NOR (8-/16-Bit-Wide Data) – 80K-Byte L1D Data RAM/Cache (2-Way • NAND (8-/16-Bit-Wide Data) Set-Associative) – 64K-Byte L2 Unified Mapped RAM/Cache • Flash Card Interfaces (Flexible RAM/Cache Allocation) – Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) – Compact Flash Controller With True IDE Mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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