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AD9869BCPZ Datasheet(PDF) 1 Page - Analog Devices |
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AD9869BCPZ Datasheet(HTML) 1 Page - Analog Devices |
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1 / 36 page  Broadband Modem Mixed-Signal Front End AD9869 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES Low cost 3.3 V CMOS MxFE for broadband modems 12-bit DAC converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 17 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS, ADC converter −12 dB to +48 dB low noise RxPGA (<3 nV/√Hz) Third-order, programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Pin compatible with the AD9866 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ APPLICATIONS Broadband wireline networking FUNCTIONAL BLOCK DIAGRAM XTAL RX– 4 6 AD9869 0 TO –7.5dB 0 TO –12dB REGISTER CONTROL CLK SYNC. ADC 80MSPS 2-4X IOUTN+ IOUTN– CLKOUT1 CLKOUT2 OSCIN RX+ IAMP TxDAC 2-POLE LPF 1-POLE LPF 0 TO 6dB Δ = 1dB –6 TO +18dB Δ = 6dB –6 TO +24dB Δ = 6dB SPI PORT AGC[5:0] PORT RXCLK RXEN/RXSYNC ADIO[11:6]/ Tx[5:0] ADIO[5:0]/ Rx[5:0] TXCLK/TXQUIET TXEN/TXSYNC MODE PWRDWN 10 10 2M CLK MULTIPLIER Figure 1. GENERAL DESCRIPTION The AD9869 is a mixed-signal front-end (MxFE®) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pin- compatible version of the AD9866, the AD9869 removes the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz. The part is well suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9869 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source. The Tx signal path consists of a 2×/4× low-pass interpolation filter, a 12-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps. The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 12-bit ADC. The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or it can be simply bypassed. The 12-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization. The AD9869 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (−40°C to +85°C). |
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