AD9868BCPZRL datasheet(6/36 Pages) AD

Part #	AD9868BCPZRL

Description	Broadband Modem Mixed-Signal Front End

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Manufacturer	AD [Analog Devices]

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AD9868

Rev. 0 | Page 6 of 36

POWER SUPPLY SPECIFICATIONS

AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V, RSET = 2 kΩ, full-duplex operation with fDATA = 80 MSPS1, unless otherwise noted.

Table 3.

Parameter

Temp

Test Level2

Min

Typ

Max

Unit

SUPPLY VOLTAGES

AVDD

Full

V

3.135

3.3

3.465

V

CLKVDD

Full

V

3.0

3.3

3.6

V

DVDD

Full

V

3.0

3.3

3.6

V

DRVDD

Full

V

3.0

3.3

3.6

V

IS_TOTAL (Total Supply Current)

Full

II

406

475

mA

POWER CONSUMPTION

IAVDD + ICLKVDD (Analog Supply Current)

Full

IV

311

342

mA

IDVDD + IDRVDD (Digital Supply Current)

Full

IV

95

133

mA

POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS)3

Tx Mode

IAVDD + ICLKVDD

25°C

IV

112

130

mA

IDVDD + IDRVDD

25°C

IV

46

49.5

mA

Rx Mode

IAVDD + ICLKVDD

25°C

IV

225

253

mA

IDVDD + IDRVDD

25°C

IV

36.5

39

mA

POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (IAVDD + ICLKVDD)

RxPGA and LPF

25°C

III

87

mA

ADC

25°C

III

108

mA

TxDAC

25°C

III

38

mA

IAMP (Programmable)

25°C

III

10

100

mA

Reference

25°C

III

170

mA

CLK PLL and Synthesizer

25°C

III

107

mA

MAXIMUM ALLOWABLE POWER DISSIPATION

Full

IV

1.66

W

STANDBY POWER CONSUMPTION

IS_TOTAL (Total Supply Current)

Full

13

mA

POWER-DOWN DELAY (Using PWRDWN Pin)

RxPGA and LPF

25°C

III

440

ns

ADC

25°C

III

12

ns

TxDAC

25°C

III

20

ns

IAMP

25°C

III

20

ns

CLK PLL and Synthesizer

25°C

III

27

ns

POWER-UP DELAY (Using PWRDWN Pin)

RxPGA and LPF

25°C

III

7.8

μs

ADC

25°C

III

88

ns

TxDAC

25°C

III

13

μs

IAMP

25°C

III

20

ns

CLK PLL and Synthesizer

25°C

III

20

μs

1 Default power-up settings for MODE = high and CONFIG = low, IOUTP_FS = 20 mA, does not include IAMP current consumption, which is application dependent.

2 See the Explanation of Test Levels section.

3 Default power-up settings for MODE = low and CONFIG = low.

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