UCC2817A, UCC2818A

UCC3817A, UCC3818A

SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

9

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APPLICATION INFORMATION

Power Stage

L

V

IN(min)

D

(

DI

f

s)

where D is the duty cycle,

circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a

equation are at the peak of low line, where the inductor current and its ripple are at a maximum.

The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage

is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed.

For this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output

power, output voltage, and holdup time gives the equation:

C

2

P

OUT

Dt

V

OUT

OUT(min)

2

In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage

specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often

necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR

allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple

current. In this design holdup time was the dominant determining factor and a 220-

µF, 450-V capacitor was

chosen for the output voltage level of 385 VDC at 250 W.

(2)

(3)