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MR2S16AVTS35C Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MR2S16AVTS35C Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 22 page MR2A16A Data Sheet, Rev. 4 8 Freescale Semiconductor Timing Specifications Timing Specifications Read Mode Table 9. Read Cycle Timing1, 2 Parameter Symbol Min Max Unit Read cycle time tAVAV 35 — ns Address access time tAVQV —35 ns Enable access time3 tELQV —35 ns Output enable access time tGLQV —15 ns Byte enable access time tBLQV —15 ns Output hold from address change tAXQX 3— ns Enable low to output active4, 5 tELQX 3— ns Output enable low to output active4, 5 tGLQX 0— ns Byte enable low to output active4, 5 tBLQX 0— ns Enable high to output Hi-Z4, 5 tEHQZ 015 ns Output enable high to output Hi-Z4, 5 tGHQZ 010 ns Byte high to output Hi-Z4, 5 tBHQZ 010 ns NOTES: 1 W is high for read cycle. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read and write cycles. 3 Addresses valid before or at the same time E goes low. 4 This parameter is sampled and not 100% tested. 5 Transition is measured ±200 mV from steady-state voltage. |
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