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MC33880DWBR2 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC33880DWBR2 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 25 page Analog Integrated Circuit Device Data 8 Freescale Semiconductor 33880 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ V DD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING Output Slew Rate Low-Side Configuration (12) RL = 620 Ω tR 0.1 0.5 1.2 V/ µs Output Slew Rate Low-Side Configuration (12) RL = 620 Ω tF 0.1 0.5 1.2 V/ µs Output Slew Rate High-Side Configuration (12) RL = 620 Ω tR 0.1 0.3 1.2 V/ µs Output Slew Rate High-Side Configuration (12) RL = 620 Ω tF 0.1 0.3 1.2 V/ µs Output Turn ON Delay Time, High-Side and Low-Side Configuration (13) tDLY(ON) 1.0 15 50 µs Output Turn OFF Delay Time, High-Side and Low-Side Configuration (13) tDLY(OFF) 1.0 30 100 µs Output Fault Delay Time (14) tFAULT 100 – 300 µs DIGITAL INTERFACE TIMING Recommended Frequency of SPI Operation – – 4.0 6.0 MHz Required Low State Duration on VDD for Reset (15) VDD ≤ 0.2 V tRESET – 4.0 10 µs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) tLEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) tLAG 50 – – ns DI to Falling Edge of SCLK (Required Setup Time) tDI(su) 16 – – ns Falling Edge of SCLK to DI (Required Hold Time) tDI(HOLD) 20 – – ns DI, CS, SCLK Signal Rise Time (16) tR(DI) – 5.0 – ns DI, CS, SCLK Signal Fall Time (16) tF(DI) – 5.0 – ns Time from Falling Edge of CS to DO Low Impedance (17) tDO(EN) – – 60 ns Time from Rising Edge of CS to DO High Impedance (18) tDO(DIS) – – 60 ns Time from Rising Edge of SCLK to DO Data Valid (19) tVALID – 25 60 ns Notes 12. Output Rise and Fall time respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points. 13. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage. 14. Duration of fault before fault bit is set. Duration between access times must be greater than 300 µs to read faults. 15. This parameter is guaranteed by design but is not production tested. 16. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 17. Time required for output status data to be available for use at DO pin. 18. Time required for output status data to be terminated at DO pin 19. Time required to obtain valid data out from DO following the rise of SCLK. |
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