3D7424-100 datasheet(4/6 Pages) DATADELAY

Part #	3D7424-100

Description	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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Manufacturer	DATADELAY [Data Delay Devices, Inc.]

Direct Link	http://www.datadelay.com

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4 / 6 page

3D7424

APPLICATION NOTES (CONT’D)

INPUT SIGNAL CONSIDERATIONS

The frequency and/or pulse width (high or low) of

operation may adversely impact the specified

delay and increment accuracy of the particular

device. The reasons for the dependency of the

output delay accuracy on the input signal

characteristics are varied and complex.

Therefore, a recommended and an absolute

maximum operating input frequency and a

recommended and an absolute minimum

operating pulse width have been specified.

OPERATING FREQUENCY

The absolute maximum operating frequency

specification, tabulated in Table 1, determines

the highest frequency of the delay line input

signal that can be reproduced, shifted in time at

the device output, with acceptable duty cycle

distortion.

The recommended maximum operating

frequency specification determines the highest

frequency of the delay line input signal for which

the output delay accuracy is guaranteed.

Operation above the recommended maximum

frequency will cause the delays to shift slighty

with respect to their values at low-frequency

operation. The magnitudes of these deviations

will increase as the absolute maximum frequency

is approached. However, if the input frequency

and pulse width remain constant, the device will

exhibit the same delays from one period to the

next (ie, no appreciable jitter).

OPERATING PULSE WIDTH

The absolute minimum operating pulse width

(high or low) specification, tabulated in Table 1,

determines the smallest pulse width of the delay

line input signal that can be reproduced, shifted

in time at the device output, with acceptable

pulse width distortion.

The minimum operating pulse width (high or low)

specification determines the smallest pulse width

of the delay line input signal for which the output

delay accuracy tabulated in Table 1 is

guaranteed.

Operation below the recommended minimum

pulse width will cause the delays to shift slighty

with respect to their values at long-pulse-width

operation. The magnitudes of these deviations

will increase as the absolute minimum pulse

width is approached. However, if the input pulse

width and frequency remain constant, the device

will exhibit the same delays from one period to

the next (ie, no appreciable jitter).

PROGRAMMED DELAY UPDATE

A delay line is a memory device. It stores

information present at the input for a time equal

to the delay setting before presenting it at the

output. Each 4-bit delay line in the 3D7424 is

represented by 15 serially connected delay

elements (individually addressed by the

programming data), each capable of storing data

for a time equal to the device increment (step

time). The delay line memory property, in

conjunction with the operational requirement of

“instantaneously” connecting the delay element

addressed by the programming data to the

output, may inject spurious information onto the

output data stream. In order to ensure that

spurious outputs do not occur, it is essential that

the input signal be idle (held high or low) for a

short duration prior to updating the programmed

delay. This duration is given by the maximum

programmable delay. Satisfying this requirement

allows the delay line to “clear” itself of spurious

edges. Once the new address is loaded, the

input signal can begin to switch.

Doc #06019

DATA DELAY DEVICES, INC.

4

6/5/2006

Tel: 973-773-2299

Fax: 973-773-9672

http://www.datadelay.com

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