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3D3622D-0.25 Datasheet(PDF) 2 Page - Data Delay Devices, Inc. |
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3D3622D-0.25 Datasheet(HTML) 2 Page - Data Delay Devices, Inc. |
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2 / 7 page  3D3622 APPLICATION NOTES GENERAL INFORMATION Figure 1 illustrates the main functional blocks of the 3D3622. Since the 3D3622 is a CMOS design, all unused input pins must be returned to well-defined logic levels, VDD or Ground. The pulse generator architecture is comprised of a number of delay cells, which are controlled by the 6 LSB bits of the address, and an oscillator & counter, which are controlled by the 16 MSB bits of the address. Each device is individually trimmed for maximum accuracy and linearity throughout the address range. The change in pulse width from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width. For dash numbers larger than 15, the 6 LSB bits are invalid, and the address loaded must therefore be a multiple of 64 (ie, 0, 64, 128, 192, etc). When used in this manner, the device is essentially a 16-bit generator, with an effective increment equal to 64 times the dash number. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. PULSE WIDTH ACCURACY There are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Pulse Width Step). The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the pulse-width-versus- address data. The INL is then the deviation of a given width from this line. For all dash numbers, the INL is within 1.0 LSB at every address. The relative error is defined as follows: erel = (tPW – tinh) – addr * tinc where addr is the address, tPW is the measured width at this address, tinh is the measured inherent width, and tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1). The absolute error is defined as follows: eabs = tPW – (tinh + addr * tinc) where tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address. The inherent pulse width error is the deviation of the inherent width from its nominal value. It is limited to 1.0 LSB or 2.0 ns, whichever is greater. PULSE WIDTH STABILITY The characteristics of CMOS integrated circuits are strongly dependent on power supply and temperature. The 3D3622 utilizes novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature. With regard to stability, the output pulse width of the 3D3622 at a given address, addr, can be split into two components: the inherent pulse width (tinh) and the relative pulse width (tPW – tinh). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. The thermal coefficient of the relative pulse width is limited to ±250 PPM/C (except for the -0.25), which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% (±9% for the dash 0.25) from the room-temperature pulse width. This holds for all dash numbers. The thermal coefficient of the inherent pulse width is nominally +20ps/C for dash numbers less than 5, and +30ps/C for all other dash numbers. The power supply sensitivity of the relative pulse width is ±1.0% (±3.0% for the dash 0.25) over the 3.0V to 3.6V operating range, with respect to the pulse width at the nominal 3.3V power supply. This holds for all dash numbers. The sensitivity of the inherent pulse width is nominally -5ps/mV for all dash numbers. It should also be noted that the DNL is also adversely affected by thermal and supply variations, particularly at the MSL/LSB crossovers (ie, 63 to 64, 127 to 128, etc). Doc #06008 DATA DELAY DEVICES, INC. 2 5/8/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |
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