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TLV320AIC32 Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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TLV320AIC32 Datasheet(HTML) 8 Page - Burr-Brown (TI) |
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8 / 87 page  www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM WCLK SDOUT BCLK SDIN td(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) TIMING CHARACTERISTICS (1) WCLK SDOUT BCLK SDIN td(WS) td(WS) td(DO-BCLK) ts(DI) th(DI) TLV320AIC32 SLAS479B – AUGUST 2005 – REVISED AUGUST 2006 Figure 2. I2S/LJF/RJF Timing in Master Mode All specifications typical at 25 °C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td (WS) ADWS/WCLK delay time 50 15 ns td (DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td BCLK to DOUT delay time 50 15 ns (DO-BCLK) ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns (1) All timing specifications are measured at characterization but not tested at final test. Figure 3. DSP Timing in Master Mode 8 Submit Documentation Feedback |
Similar Part No. - TLV320AIC32_07 |
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Similar Description - TLV320AIC32_07 |
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