Philips Semiconductors

Product specification

PCK2510S

50–150 MHz 1:10 SDRAM clock driver

1999 Dec 13

5

SYMBOL

PARAMETER

CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

3

3.6

V

HIGH level input voltage

2

V

LOW level input voltage

0

0.8

V

Input voltage

0

V

Operating ambient temperature range in free air

0

+70

°C

NOTE:

1. Unused inputs must be held high or low to prevent them from floating.

ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range (unless otherwise noted)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

OTHER

MIN

TYP

MAX

UNIT

Input clamp voltage

3

–1.2

V

MIN to MAX

HIGH level output voltage

3

2.1

V

3

2.4

MIN to MAX

–

0.2

LOW level output voltage

3

–

0.8

V

3

–

0.55

Input current

3.6

±5

µA

Quiescent supply current

3.6

10

µA

30

50

µA

Additional supply current per

input pin

3.3 to 3.6

500

µA

Input capacitance

3.3

2.8

pF

Output capacitance

3.3

5.4

pF

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature

SYMBOL

PARAMETER

MIN

MAX

UNIT

Clock frequency

50

150

MHz

Input clock duty cycle

40

60

%

1

ms

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation

delay, skew, and jitter parameters given in the switching characteristics table are not applicable.