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PCK2509S Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCK2509S Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 10 page Philips Semiconductors Product specification PCK2509S 50–150 MHz 1:9 SDRAM clock driver 1999 Oct 19 6 TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature. SYMBOL PARAMETER MIN MAX UNIT fCLK Clock frequency 50 150 MHz Input clock duty cycle 40 60 % Stabilization time1 1 ms NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS Over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF 1 PARAMETER FROM TO VCC, AVCC = 3.3 V ±0.3 V UNIT PARAMETER (INPUT)/CONDITION (OUTPUT) MIN TYP MAX UNIT t 2 CLKIN ↑ = 100 MHz to 133 MHz FBIN ↑ –100 100 ps tphase error 2 CLKIN ↑ = 66 MHz FBIN ↑ –125 125 ps tphase error, – jitter 3 CLKIN ↑ = 100 MHz to 133 MHz FBIN ↑ –50 50 ps tSK(0) 4 Any Y or FBOUT Any Y or FBOUT 200 ps jitter(peak-peak) CLKIN = 66 MHz to 133 MHz Any Y or FBOUT –80 80 ps jitter (cycle-cycle) CLKIN = 66 MHz to 133 MHz Any Y or FBOUT |65| ps Duty cycle reference F(CLKIN > 60 MHz) Any Y or FBOUT 47 53 % tr VO = 0.4 to 2 V Any Y or FBOUT 2.5 1 V/ns tf VO = 0.4 to 2 V Any Y or FBOUT 2.5 1 V/ns NOTES: 1. These parameters are not production tested. 2. This is considered as static phase error. 3. Phase error does not include jitter. (tphase error = static tphase error – jitter (cycle-cycle)). 4. The tSK(0) specification is only valid for equal loading of all outputs. PARAMETER MEASUREMENT INFORMATION SW00384 3V 0V VOH VOL OUTPUT INPUT 50% VCC 50% VCC tf tr 2V 0.4V 2V 0.4V FROM OUTPUT UNDER TEST 30pF 500 Ω LOAD CIRCUIT FOR OUTPUTS VOLTAGE WAVEFORMS & PHASE ERROR TIMES NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, ZO = 50Ω , tr ≤ 1.2ns, tf ≤ 1.2ns. 3. The outputs are measured one at a time with one transition per measurement. tpe Figure 1. Load Circuit and Voltage Waveforms |
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