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IS23SC1604-X2I Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc |
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IS23SC1604-X2I Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc |
5 / 18 page Integrated Silicon Solution, Inc. — 1-800-379-4774 5 ADVANCE INFORMATION Rev. 00E 04/10/03 IS23SC1604 ISSI® Device Operations (1) Operation FUS PGM RST CLK Description Reset X X 0 The address counter is reset to zero and the first bit of the memory is output after the falling edge of RST. INC/Read X 0 0 The address counter is incremented and the first bit is output after the falling edge of the clock if read access to the bit location is enabled. INC/CMP X 0 0 Compare the input bit with the internal bit of the memory (for Security/Erase Key codes validation). The address counter is incremented on the falling edge of CLK. The input bit is latched into the device at the rising edge of CLK and the bit comparison is done on the next falling edge of CLK. Erase/Write X 1 0 For write operation (write a ‘0’ to the current address), a ‘0’ is placed on I/O before the rising edge of CLK. For erase byte operation (write FFH to the byte that contains the current bit), a ‘1’ is placed on I/O before the rising edge of CLK. CLK must stay HIGH for 5 ms during memory programming. Verify X 0 0 The new content of the current address will be output after the falling edge of CLK for verification. Standby 0 0 1 X The device is placed into standby mode. In this mode, the address counter will not be incremented with clock pulse when RST is HIGH. Note: 1. X = Don’t Care. |
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