Philips Semiconductors

Preliminary specification

PCK2010

CK98 (100/133MHz) Spread Spectrum System Clock

Generator

1999 Mar 01

9

AC CHARACTERISTICS

CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133MHz MODE

100MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

CPUCLK period

7.5

8.0

10.0

10.5

ns

2, 9

CPUCLK HIGH time

1.87

n/a

3.0

n/a

ns

5, 10

CPUCLK LOW time

1.67

n/a

2.8

n/a

ns

6, 10

CPUCLK rise time

0.4

1.6

0.4

1.6

ns

8

CPUCLK fall time

0.4

1.6

0.4

1.6

ns

8

CPUCLK cycle-cycle jitter

250

250

ps

DUTY CYCLE

Output Duty Cycle

45

55

45

55

%

1

CPUCLK pin-pin skew

175

175

ps

2

CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0–1) (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133MHz MODE

100MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

CPUDIV2 CLK period

15.0

16.0

20.0

21.0

ns

2, 9

CPUDIV2 CLK HIGH time

5.25

n/a

7.5

n/a

ns

5, 10

CPUDIV2 CLK LOW time

5.05

n/a

7.3

n/a

ns

6, 10

CPUDIV2 CLK rise time

0.4

1.6

0.4

1.6

ns

8

CPUDIV2 CLK fall time

0.4

1.6

0.4

1.6

ns

8

CPUDIV2 CLK cycle-cycle jitter

250

250

ps

DUTY CYCLE

CPUDIV2 CLK Duty Cycle

45

55

45

55

%

1

CPUDIV2 CLK pin-pin skew

175

175

ps

2

PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133MHz MODE

100MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

PCICLK period

30.0

n/a

30.0

n/a

ns

2, 9

PCICLK HIGH time

12.0

n/a

12.0

n/a

ns

5, 10

PCICLK LOW time

12.0

n/a

12.0

n/a

ns

6, 10

PCICLK rise time

0.5

2.0

0.5

2.0

ns

8

PCICLK fall time

0.5

2.0

0.5

2.0

ns

8

PCICLK cycle-cycle jitter

500

500

ps

DUTY CYCLE

PCICLK Duty Cycle

45

55

45

55

%

1

PCICLK pin-pin skew

500

500

ps

2