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ATTINY45 Datasheet(PDF) 5 Page - ATMEL Corporation |
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ATTINY45 Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 201 page  5 7598D–AVR–02/07 ATtiny25/45/85 Auto 2.3 Pin Descriptions 2.3.1 VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 54. On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15. 2.3.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 36. Shorter pulses are not guaranteed to generate a reset. 3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. |
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