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1389CS–CASIC–06-Nov-06

ATC18 Summary

3.

Input/Output Pad Cell Libraries IO18lib, IO25lib and IO33lib

The Atmel Input/Output Cell Library IO18lib contains a comprehensive list of input, output, bi-

directional and tristate cells. The ATC18 (1.8V) cell library includes a special set of I/O cells,

IO25lib (IO33lib), for interfacing with external 2.5V (3.3V) devices.

3.1

Voltage Levels

The IO18lib library is made up exclusively of low-voltage chip interface circuits powered by a

voltage level in the range of 1.65V to 1.95V. The library is compatible with SClib, 1.8-volt stan-

dard cell library.

3.2

Power and Ground Pads

Designers are strongly encouraged to provide three kinds of power pairs for the IO18lib library.

These are “AC”, “DC” and core power pairs. AC power is used by the I/O to switch its output

from one state to the other. This switching generates noise in the AC power buses on the chip.

DC power is used by the I/O to maintain its output in a steady state. The best noise performance

is achieved when the DC power buses on the chip are free of noise; you are encouraged to use

separate power pairs for AC and DC power to prevent most of the noise in the AC power buses

from reaching the DC power buses. You can use the same power pairs to supply both DC power

to the I/Os and power to the core without affecting noise performance.

Table 3-1.

VSS Power Pad Combinations

Core

Switching I/O

Quiet I/O

Library Cell Name

Signal Name

Vssi/gnd

VssAC

VssDC

•/ •

pv18i00

VSS

•

pv18a00

VSS

•

pv18d00

VSS

••

pv18e00

VSS

•/ •

•

pv18b00

VSS

•/ •

•

•

pv18f00

VSS

/•

pv18c00

VSS

Table 3-2.

VDD Power Pad Combinations

Core

Switching I/O

Quiet I/O

Library Cell Name

Signal Name

Vddi/vdd

VddAC

VddDC

•/ •

pv18i18

VDD

•

pv18a18

VDD

•

pv18d18

VDD

••

pv18e18

VDD

•/ •

•

pv18b18

VDD

•/ •

•

•

pv18f18

VDD

/•

pv18c18

VDD