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1389CS–CASIC–06-Nov-06

ATC18 Summary

7.

Compiled CMOS Memories

The Atmel CMOS Memory Compiler Library enables users to compile memories for the func-

tions Single-port Synchronous RAM, Dual-port Synchronous RAM, Via Programmable ROM and

Two-port Synchronous Register File according to their precise requirements. Memories com-

piled in this way can be instanced as often as required in designs, alongside cells from other

Atmel CBIC libraries.

7.1

Single-port Synchronous SRAM

Key features of the single-port synchronous SRAM are:

• High-density (HD) SRAM

• 350 MHz worst-case cycle time

• Zero Quiescent Current

• 3-state outputs

• Several aspect ratios for optimization

• Separate Data-in, Data-out pins support a write-through feature

• Asynchronous write-through for testing interface shadow logic

•BIST interface

• Optional Sub-word write decode

The single-port SRAM compiler is a high-density RAM compiler with quiescent current consump-

tion equal to zero when the SRAM is not in a read or write mode. The compiler is optimized for a

power supply voltage range of 1.62V to 1.98V and can operate at voltages as low as 1.2V. The

SRAM instances can be built with several aspect ratios for maximum area and performance opti-

mization. Separate output (Q) and input (D) pins allow a write-through cycle feature. An

asynchronous write through mode (AWT) allows testing of interface shadow logic. Built-in BIST

interface allows for easy connection to most memBIST solutions. The special test modes allow

externally bypassing read and write self-timed circuits and adjusting read and write margins. The

SRAM memory also includes a sub-word feature where selective write to each group of 8-bit

subwords can be done. A maskable write enable signal is provided for each 8-bit group.

Table 7-1 gives the range of permitted single-port synchronous RAM configurations.

Note:

1. CM = 4, 8, 16: Column Mux option

7.2

Dual-port Synchronous RAM

Key features of the dual-port synchronous RAM are:

• High-density (HD) SRAM

• 300 MHz worst-case cycle time

• Zero Quiescent Current

• 3-state outputs

Table 7-1.

Configuration Range

Parameter

Min

Max

Increment

Address Locations (words)

32

16K

Word Size (Number of I/O bits)

2

128

1 bit

Total Bits in Core (Word Size x Address Locations)

128

512K