PCD5042HZ datasheet(4/28 Pages) PHILIPS

Part #	PCD5042HZ

Description	DECT burst mode controller

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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4 / 28 page

1996 Oct 31

4

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5042

4

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MBH741

RF INTERFACE

PROGRAMMABLE

COMMUNICATION

CONTROLLER (PCC)

DATA MEMORY

2 kbyte RAM

TIMING, CONTROL,

CLOCK

GENERATION

PCC

PROGRAM MEMORY

4 kbyte ROM

MICROCONTROLLER

INTERFACE

SPEECH

INTERFACE

internal

bus

PCD5042

DECT

BURST MODE

CONTROLLER

to CODEC/

Highway

3-wire synthesizer

interface

Rx/Tx data

8051/68000

interface

5

PINNING (see Figs 2 and 3)

SYMBOL

TYPE(2)

DESCRIPTION

QFP64

LQFP80(1)

AD0 to AD7

1 to 8

80, 1, and

3to 7

I/O

address/Data bus

ALE

9

I

address latch enable

CS

10

11

I

chip select (active LOW)

A8 to A10

13 to 11

14 to 12

I

address bus

VDD1

14

15

P

positive supply 1

PROC_CLK

15

16

O

microcontroller clock; programmable from fCLK/64 to fCLK,

where fCLK is the crystal oscillator frequency

VSS1

16

17

P

negative supply 1

XTAL1

17

20

I

crystal oscillator input

XTAL2

18

21

O

crystal oscillator output

VSS2

19

22

P

negative supply

RESET_OUT

20

23

O

watchdog timer output; intended to reset the external

microcontroller when expired

RD

21

24

I

read (active LOW)

WR

22

25

I

write (active LOW)

RDY

23

26

O

ready signal (active LOW), to initiate wait states in the

microcontroller (open drain)

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PCD5042HZ Datasheet(PDF) 4 Page - NXP Semiconductors

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