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SMJ55161 Datasheet(PDF) 8 Page - Texas Instruments |
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SMJ55161 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 64 page  SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pin definitions Table 2. Pin Description Versus Operational Mode PIN DRAM TRANSFER SAM A0 – A8 Row, column address Row address, tap point CASL CASU Column-address strobe, DQ output enable Tap-address strobe DQ DRAM data I/O, write mask DSF Block-write enable Write-mask-register load enable Color-register load enable CBR (option reset) Split-register-transfer enable RAS Row-address strobe Row-address strobe SE SQ output enable, QSF output enable SC Serial clock SQ Serial-data output TRG DQ output enable Transfer enable WE Write enable, write-per-bit enable QSF Special-function output Serial-register status NC/GND Either make no external connection or tie to system GND (VSS) VCC† 5-V supply VSS† Ground † For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground. address (A0 – A8) Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address bits are set up on pins A0 – A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set up on pins A0 – A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on or before the falling edge of RAS and the first falling edge of CASx. During the full-register-transfer read operation, the states of A0 – A8 are latched on the falling edge of RAS to select one of the 512 rows where the transfer occurs. At the first falling edge of CASx, the column-address bits A0 –A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred to the SAM. The appropriate 8-bit column address (A0 –A7) selects one of 256 tap points (starting positions) for the serial-data output. During the split-register-transfer read operation, address bit A7 is ignored at the falling edge of CASx. An internal counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM half row. The remaining seven address bits (A0 –A6) are used to select one of 127 possible starting locations within the SAM. Locations 127 and 255 are not valid tap points. row-address strobe (RAS) RAS is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of RAS. RAS is a control input that latches the states of the row address, WE, TRG, CASL, CASU, and DSF onto the chip to invoke DRAM and transfer-read functions of the SMJ55161. |
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