FIGURE 1 - BLOCK DIAGRAM

TYPICAL CHANNEL

DIFF

AMP

OUTA

OUTB

PLUS

MINUS

TESTA

TESTB

INA

CAPA

INB

CAPB

Comp

+Vs

LEVEL

SHIFT

LEVEL

SHIFT

-Vs

GND

Comparators

w / hysteresis

Comp

Detect

Level

Detect

Level

FUNCTIONAL DESCRIPTION

The HI-8482 contains two independent ARINC 429 receive

channels. The diagram in Figure 1 illustrates a typical HI-

8482 receive channel.

The differential ARINC signal input is converted to a positive

signal referenced to ground through level shifters and a

unity gain differential amplifier.

A positive differential input signal is converted to a positive

signal on the plus output of the differential amplifier. This

output is proportional in amplitude to the original input

signal. At the same time, the corresponding MINUS output

is pulled to GND. Likewise when a negative input signal is

present at the ARINC inputs, a positive signal is present on

the MINUS output and the PLUS output is pulled to GND.

The outputs of the differential amplifier are compared with

the ONE, ZERO and NULL threshold levels to produce the

appropriate logic level on the OUTA and OUTB outputs of

the device.

The ARINC clock signal may be recovered

through a NOR function of OUTA and OUTB.

The test inputs logically disconnect the outputs of the

comparators from OUTA and OUTB and force the device

outputs to one of the three valid states (Figure 5). This

alleviates having to ground the ARINC inputs during test

mode operation.

ARINC LEVELS

The ARINC 429 specification requires the following

detection levels:

ONE

+6.5V to +13V

NULL

+2.5V to -2.5V

ZERO

-6.5V to -13V

The HI-8482 guarantees recognition of these levels with a

common mode voltage with respect to GND less than

±5V for the worst case condition.

STATE

DIFFERENTIAL VOLTAGE

NOISE

The input hysteresis is set to reject voltage level transi-

tions in the undefined region between the maximum

ZERO level and the minimum NULL level and the unde-

fined region between the maximum NULL level and the

minimum ONE level.

Therefore, once a valid input

differential voltage threshold is detected, the outputs will

remain at a valid logic state until a new valid input voltage

is detected.

In addition to the hysteresis, the CAPA and CAPB pins

make it possible to add simple RC filters to the ARINC

inputs.

HI-8482

HOLT INTEGRATED CIRCUITS

2