Philips Semiconductors

Product data

PCA9557

2

2001 Dec 12

853-2308 27449

FEATURES

PCA9556

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

exceeds 100 mA

DESCRIPTION

The PCA9557 is a silicon CMOS circuit which provides parallel

PCA9557 consists of an 8-bit input port register, 8-bit output port

consumption and a high impedance open drain output pin, I/O0.

The system master can enable the PCA9557’s I/O as either input or

output by writing to the configuration register.

The system master can also invert the PCA9557 inputs by writing to

the active HIGH polarity inversion register.

Finally, the system master can reset the PCA9557 in the event of a

timeout by asserting a LOW in the reset input.

The power-on reset puts the registers in their default state and

same reset/initialization to occur without depowering the part.

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

su01045

SCL

SDA

A0

A1

A2

I/O0

I/O1

RESET

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

Figure 1. Pin configuration

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

1

SCL

Serial clock line

2

SDA

Serial data line

3

A0

Address input 0

4

A1

Address input 1

5

A2

Address input 2

6

I/O0

I/O0 (open drain)

7

I/O1

I/O1

8

Supply ground

9

I/O2

I/O2

10

I/O3

I/O3

11

I/O4

I/O4

12

I/O5

I/O5

13

I/O6

I/O6

14

I/O7

I/O7

15

RESET

Active low reset input

16

Supply voltage

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

16-Pin Plastic SO (narrow)

–40 to +85

°C

PCA9557D

SOT109-1

16-Pin Plastic TSSOP

–40 to +85

°C

PCA9557PW

SOT403-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.