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PCA8550 Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCA8550 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM 2 1998 Sep 29 853-2015 20105 FEATURES •4-bit 2-to-1 multiplexer, 1-bit latch •5-bit internal non-volatile register •Override input forces all outputs to logic 0 •Internal non-volatile register write/readable via I2C bus •Write-protect pin enables/disables I2C writes to register •2.5V multiplexed outputs •3.3V non-multiplexed output (latched) •5V tolerant inputs •Useful for ’jumperless’ configuration of PC motherboards •Designed for use in Pentium Pro/Pentium II™ systems Pentium II is a registered trademark of Intel Corporation DESCRIPTION The primary function of the 4-bit 2-to-1 I2C multiplexer is to select either a 4-bit input or data from a non-volatile register and drive this value onto the output pins. One additional non-multiplexed register output is also provided. The non-multiplexed output is latched to prevent output value changes during I2C writes to the non-volatile register. A write protect input is provided to enable/disable the ability to write to the non-volatile register. An ‘‘override” input feature forces all outputs to logic 0. PIN CONFIGURATION I 2C SCL I2C SDA OVERRIDE# MUX_IN A GND VCC WP NON_MUXED_OUT 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 MUX_IN B MUX_IN C MUX_IN D MUX_SELECT MUX_OUT A MUX_OUT B MUX_OUT C MUX_OUT D SW00216 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 16-Pin Plastic SO 0 °C to +70°C PCA8550D PCA8550D SOT109-1 16-Pin Plastic SSOP 0 °C to +70°C PCA8550DB PCA8550DB SOT338-1 16-Pin Plastic TSSOP 0 °C to +70°C PCA8550PW PCA8550PW DH SOT403-1 FUNCTIONAL DESCRIPTION When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1. The write protect (WP) input is used to control the ability to write the contents of the 5-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. |
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