www.ti.com

FUNCTIONAL DESCRIPTION

Serialization Modes

1-Channel Mode

D0+/– CHANNEL

CLK+

B7 B6

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0

B5 B4 B3 B2 B1 B0 VS HS DE

0

0

CP R7 R6

CP

0

0

CLK–

2-Channel Mode

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS

0

CP

0

B7 B6

G3 G2 G1 G0

B5 B4 B3 B2 B1 B0 HS DE

0

CP

R7 R6

G3 G2

CLK+

CLK–

D0+/– Channel

D1+/– Channel

Power-Down Modes

Shutdown Mode

SN65LVDS303

SLLS743A – JULY 2006 – REVISED JANUARY 2007

The SN65LVDS303 transmitter has two modes of operation controlled by link-select terminal LS. Table 3 shows

the serializer modes of operation.

Table 3. Logic Table: Link Select Operating Modes

LS

Mode of Operation

Data Links Status

0

1-channel mode, 1ChM (30-bit serialization rate)

D0 active; D1 high-impedance

1

2-channel mode, 2ChM (15-bit serialization rate)

D0, D1 active

While LS is held low, the SN65LVDS303 transmits payload data over a single SubLVDS data pair, D0. The PLL

locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is used to

serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data frame.

Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-speed

clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output. While

in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode is intended

for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth capabilities of the

SN65LVDS303.

Figure 3. Data and Clock Output in 1-Channel Mode (LS = Low).

While LS is held high, the SN65LVDS303 transmits payload data over two SubLVDS data pairs, D0 and D1. The

PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed clock is used to serialize

the data payload on D0 and D1. Two reserved bits and the parity bit are added to the data frame. Figure 4

illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split

into the two output channels. The internal high-speed clock is divided by 15 to recreate the pixel clock and

presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz through 30 MHz in this

mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.

Figure 4. Data and Clock Output in 2-Channel Mode (LS = High).

The SN65LVDS303 transmitter has two power-down modes to facilitate efficient power management.

The SN65LVDS303 enters shutdown mode when the TXEN terminal is asserted low. This turns off all

transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All

outputs are high-impedance. Current consumption in shutdown mode is nearly zero.

7

Submit Documentation Feedback