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TSC2007IYZGR Datasheet(PDF) 7 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part # TSC2007IYZGR
Description  1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with I2C Interface
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

TSC2007IYZGR Datasheet(HTML) 7 Page - Burr-Brown (TI)

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TIMING REQUIREMENTS: I2C Fast Mode (SCL = 400kHz)
TSC2007
SBAS405 – MARCH 2007
All specifications typical at –40
°C to +85°C, V
DD = 1.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL clock frequency
fSCL
0
400
kHz
Bus free time between a STOP and START condition
tBUF
1.3
µs
Hold time (repeated) START condition
tHD, STA
0.6
µs
Low period of SCL clock
tLOW
1.3
µs
High period of the SCL clock
tHIGH
0.6
µs
Setup time for a repeated START condition
tSU, STA
0.6
µs
Data hold time
tHD, DAT
0
0.9
µs
Data setup time
tSU, DAT
100
ns
Rise time for both SDA and SCL clock signals (receiving)
tR
Cb = total bus capacitance
20+0.1
×C
b
300
ns
Fall time for both SDA and SCL clock signals (receiving)
tF
Cb = total bus capacitance
20+0.1
×C
b
300
ns
Fall time for both SDA and SCL clock signals (transmitting)
tOF
Cb = total bus capacitance
20+0.1
×C
b
250
ns
Setup time for STOP condition
tSU, STO
0.6
µs
Capacitive load for each bus line
Cb
Cb = total capacitance of one bus line in pF
400
pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
134.7
µs
Cycle time
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
203.4
µs
8 bits
VDD = 1.8V
7.42
kSPS
Effective throughput
12 bits
VDD = 1.8V
4.92
kSPS
8 bits
VDD = 1.8V
51.97
kHz
Equivalent rate = effective throughput
× 7
12 bits
VDD = 1.8V
34.42
kHz
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 1.7MHz)
All specifications typical at –40
°C to +85°C, V
DD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL clock frequency
fSCL
0
1.7
MHz
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
320
ns
High period of the SCL clock
tHIGH
120
ns
Setup time for a repeated START condition
tSU, STA
160
ns
Data hold time
tHD, DAT
0
150
ns
Data setup time
tSU, DAT
10
ns
Rise time for SCL clock signal (receiving)
tR
Cb = total bus capacitance
20
80
ns
Rise time for SDA clock signal (receiving)
tR
Cb = total bus capacitance
20
160
ns
Fall time for SCL clock signal (receiving)
tF
Cb = total bus capacitance
20
80
ns
Fall time for SDA clock signal (receiving)
tF
Cb = total bus capacitance
20
160
ns
Fall time for both SDA and SCL clock signals (transmitting)
tOF
Cb = total bus capacitance
10
80
ns
Setup time for STOP condition
tSU, STO
160
ns
Capacitive load for each bus line
Cb
Cb = total capacitance of one bus line in pF
400
pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
58.2
µs
Cycle time
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
109.7
µs
8 bits
VDD = 1.8V
17.17
kSPS
Effective throughput
12 bits
VDD = 1.8V
9.12
kSPS
8 bits
VDD = 1.8V
120.22
kHz
Equivalent rate = effective throughput
× 7
12 bits
VDD = 1.8V
63.81
kHz
7
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