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TPS62350YZG Datasheet(PDF) 7 Page - Texas Instruments |
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TPS62350YZG Datasheet(HTML) 7 Page - Texas Instruments |
7 / 46 page www.ti.com I2C TIMING DIAGRAMS tf tLOW tr thd;STA thd;DAT tsu;DAT tf HIGH tsu;STA S Sr P S thd;STA tr tBUF tsu;STO SDA SCL Sr P Sr tfDA trDA thd;DAT tsu;STA thd;STA tsu;DAT tsu;STO trCL1 tfCL tHIGH tLOW tLOW tHIGH trCL trCL1 = MCS Current Source Pull-Up = R(P) Resistor Pull-Up SDAH SCLH Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit. See Note A See Note A TPS62350, TPS62351 TPS62352, TPS62353, TPS62354 SLVS540B – MAY 2006 – REVISED DECEMBER 2006 I2C INTERFACE TIMING CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns tFDA Fall Time of SDA Signal High-speed mode, CB– 100 pF max 10 80 ns High-speed mode, CB– 400 pF max 20 160 ns Standard mode 4 µs tSU, tSTO Setup Time for STOP Condition Fast mode 600 ns High-speed mode 160 ns CB Capacitive Load for SDA and SCL 400 pF Figure 1. Serial Interface Timing Diagram for F/S-Mode Figure 2. Serial Interface Timing Diagram for HS-Mode 7 Submit Documentation Feedback |
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