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TMS320DM647ZUT720 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320DM647ZUT720 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 166 page  www.ti.com 2 Device Overview 2.1 Device Characteristics TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 Table 2-1, provides an overview of the TMS320DM647/TMS320DM648 DSPs. The tables show significant features of the DM647/DM648 devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the DM647/DM648 Processor HARDWARE FEATURES DM647 DM648 DDR2 memory controller (32-bit bus 1 1 width) [1.8 V I/O] 16-bit bus width synchronous/asynchronous EMIF 1 1 [EMIFA] EDMA3 (64 independent channels, 8 1 1 QDMA channels) 4 64-bit General Purpose 4 64-bit General Purpose Timers (each configurable as 1 64-bit or 2 (each configurable as 1 64-bit or 2 32-bit) 32-bit) UART (with RTS and CTS flow control) (with RTS and CTS flow control) Peripherals I2C 1 (Master/Slave) 1 (Master/Slave) Not all peripheral pins are available SPI 1 (4-wire, 2 chip select) 1 (4-wire, 2 chip select) at the same time McASP 1 (10 serailizers) 1 (10 serailizers) (For more detail, see Section 3.) 3-port Ethernet Switch Subsystem supporting 10/100/1000 Base-T 1 SGMII port available 2 SGMII ports available Management data input/output (MDIO) VLYNQ 1 1 General-purpose input/output port Up to 32 pins Up to 32 pins (GPIO) HPI (16/32-bit) 1 1 PCI (32 bit) (33 MHz or 66 MHz) 1 (PCI33 or PCI66) 1 (PCI33 or PCI66) VIC 1 1 Configurable video ports 5 5 Size (bytes) 320KB RAM, 64KB ROM 576KB RAM, 64KB ROM 32KB L1 program (L1P)/cache (Cache 32KB L1 program (L1P)/cache (up to up to 32KB) 32KB) 32KB L1 data (L1D)/cache (Cache up 32KB L1 data (L1D)/cache (up to On-Chip Memory Organization to 32KB) 32KB) 256KB unified mapped RAM/Cache 512 KB unified mapped RAM/Cache (L2) (L2) 64KB Boot ROM 64KB Boot ROM Revision ID Register MegaModule Rev (MM_REVID[15:0]) 0x0003 0x0003 ID (address location 0x0181 2000) CPU ID + CPU Control Status Register (CSR.[31:16]) 0x1000 0x1000 Rev ID JTAGID register JTAG BSDL_ID 0x0B77 A02F 0x0B77 A02F (address location: 0x0204 9018) CPU Frequency MHz 720, 900 720, 900 Cycle Time ns 1.39 ns (-720), 1.11 ns (-900) 1.39 ns (-720), 1.11 ns (-900) Core (V) 1.2 V (-720, 900) 1.2 V (-720, 900) Voltage I/O (V) 1.8 V, 3.3 V 1.8 V, 3.3 V PLL Options CLKIN1 frequency multiplier x1 (Bypass), x15, x20, x25, x30, x32 x1 (Bypass), x15, x20, x25, x30, x32 BGA Package 529-Pin Flip Chip Plastic BGA (ZUT) 529-Pin Flip Chip Plastic BGA (ZUT) Device Overview 6 Submit Documentation Feedback |
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