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ISL8103CRZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL8103CRZ Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 27 page  7 FN9246.0 February 15, 2006 Timing Diagram Simplified Power System Diagram Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V supply and locally decouple using a quality 1.0 µF ceramic capacitor. PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18) Power supply pins for the corresponding channel MOSFET drive. These pins can be connected to any voltage from +5V to +12V, depending on the desired MOSFET gate drive level. Note that tying PVCC2 OR PVCC3 to GND has the same effect as tying 2PH or 3PH to GND for disabling the corresponding phase GND (Pin 41) Bias and reference ground for the IC. ENLL (Pin 37) This pin is a threshold sensitive (approximately 0.66V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation. FS (Pin 36) A resistor, placed from FS to ground, will set the switching frequency. Refer to Equation 33 and Figure 23 for proper resistor calculation 3PH and 2PH (Pins 1, 2) These pins decide how many phases the controller will operate. Tying both pins to VCC allows for 3-phase operation. Tying the 3PH pin to GND causes the controller to operate in 2-phase mode, while connecting both 3PH and 2PH GND will allow for single phase operation. UGATE LGATE tFLGATE tPDHUGATE tRUGATE tFUGATE tPDHLGATE tRLGATE CHANNEL1 +5VIN VOUT Q1 Q2 ISL8103 CHANNEL2 Q3 Q4 DAC CHANNEL3 Q5 Q6 +12VIN ENLL PGOOD 2 REF0,REF1 OVP ISL8103 |
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