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ISL6310IRZ Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6310IRZ Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 27 page 10 FN9209.3 December 12, 2006 s 25 and 26 in the section entitled See “Input Capacitor Selection” on page 24. can be used to determine the input- capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6310 is two. One switching cycle is defined as the time between the internal PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands PWM1 to go low. The PWM1 transition signals the internal channel 1 MOSFET driver to turn off the channel 1 upper MOSFET and turn on the channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/2 of a cycle after the PWM1 pulse. One switching cycle for the ISL6310 is defined as the time between consecutive PWM pulse terminations (turn-off of the upper MOSFET on a channel). Each cycle begins when a switching clock signal commands the upper MOSFET to go off. The other channel’s upper MOSFET conduction is terminated 1/2 of a cycle later. Once a PWM pulse transitions low, it is held low for a minimum of 1/3 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 3. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The internal MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Single phase operation can be selected by connecting 2PH to GND. Channel Current Balance One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials. In order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry about the same amount of current at any load level. To achieve this, the currents through each channel must be sampled every switching cycle. The sampled currents, In, from each active channel are summed together and divided by the number of active channels. The resulting cycle average current, IAVG, provides a measure of the total load- current demand on the converter during each switching cycle. Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current balance method is illustrated in Figure 3, with error correction for channel 1 represented. In the figure, the cycle average current, IAVG, is compared with the Channel 1 sample, I1, to create an error signal IER. The filtered error signal modifies the pulse width commanded by VCOMP to correct any unbalance and force IER toward zero. The same method for error signal correction is applied to each active channel. Current Sampling In order to realize proper current balance, the currents in each channel must be sampled every switching cycle. This sampling occurs during the forced off-time, following a PWM FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT- CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER Q1 D-S CURRENT Q2 D-S CURRENT CIN CURRENT FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT- BALANCE ADJUSTMENT ÷ N IAVG I2 Σ - + + - + - f(s) PWM1 I1 VCOMP SAWTOOTH SIGNAL IER NOTE: Channel 2 is optional. FILTER TO GATE CONTROL LOGIC ISL6310 |
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