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CDCDLP223 Datasheet(PDF) 4 Page - Texas Instruments |
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CDCDLP223 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 9 page www.ti.com TIMING REQUIREMENTS (1) CDCDLP223 SCAS836 – DECEMBER 2006 over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN TYP MAX UNIT XIN, XOUT REQUIREMENTS fXIN Frequency of crystal attached to XIN, XOUT, with CL = 20 pF (2 × 40 pF) on-die 20 MHz capacitance 2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE fSCLK SCLK frequency 0 100 kHz th(START) START hold time (see Figure 1) 4.0 µs tw(SCLL) SCLK low-pulse duration (see Figure 1) 4.7 µs tw(SCLH) SCLK high-pulse duration (see Figure 1) 4.0 µs tsu(START) START setup time (see Figure 1) 4.7 µs th(SDATA) SDATA hold time (see Figure 1) 0 3.45 µs tsu(SDATA) SDATA setup time (see Figure 1) 250 ns tr(SDATA) SCLK / SDATA input rise time (see Figure 1) 1000 ns tf(SDATA) SCLK / SDATA input fall time (see Figure 1) 300 ns tsu(STOP) STOP setup time (see Figure 1) 4.0 µs tBUS Bus free time 4.7 µs 2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE fSCLK SCLK frequency 0 400 kHz th(START) START hold time (see Figure 1) 0.6 µs tw(SCLL) SCLK low-pulse duration (see Figure 1) 1.3 µs tw(SCLH) SCLK high-pulse duration (see Figure 1) 0.6 µs tsu(START) START setup time (see Figure 1) 0.6 µs th(SDATA) SDATA hold time (see Figure 1) 0 0.9 µs tsu(DATA) SDATA setup time (see Figure 1) 100 ns tr(SDATA) SCLK / SDATA input rise time (see Figure 1) 20 300 ns tf(SDATA) SCLK / SDATA input fall time (see Figure 1) 20 300 ns tsu(STOP) STOP setup time (see Figure 1) 0.6 µs tBUS Bus free time 1.3 µs (1) The CDCDLP223 2-wire serial interface in Send-Mode meets both I2C and SMBus set up time tsu and hold time th requirements. 4 Submit Documentation Feedback |
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Similar Description - CDCDLP223_07 |
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