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DEVICE CHARACTERISTICS

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MAX

UNIT

OVERALL PARAMETER

All PLLs on, all outputs on,

90

115

mA

Power down current. Every circuit

50

µA

powered down except SMBus

2.1

V

power up control circuit

All PLLs

80

200

VCO frequency of internal PLL (any

PLL2 with SSC

80

167

MHz

of three PLLs)

180

300

250

MHz

See Figure 4

300

LVCMOS PARAMETER

LVCMOS input voltage

–1.2

V

LVCMOS input current (CLK_IN0 and

±5

µA

CLK_IN1)

LVCMOS input current (S1/S0)

5

µA

LVCMOS input current (S1/S0)

-35

-10

µA

Input capacitance at CLK_IN0 and

3

pF

CLK_IN1

2.9

LVCMOS high-level output voltage

2.4

V

2.1

0.1

LVCMOS low-level output voltage

0.5

V

0.85

All PLL bypass

9

Propagation delay

ns

VCO bypass

11

Rise and fall time for output

1.7

3.3

4.8

ns

slew rate 0

Rise and fall time for output

1.5

2.5

3.2

ns

slew rate 1

Rise and fall time for output

1.2

1.6

2.1

ns

slew rate 2

Rise and fall time for output

0.4

0.6

1

ns

slew rate 3 (default configuration)

55

90

1 PLL, 1 Output

45

80

ps

125

155

3 PLLs, 3 Outputs

60

95

(1)

(2)

For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using high-speed mode of the VCO reduces

the current consumption. See Figure 3.

(3)

lower but impacts jitter-performance.

(4)

Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow). See Figure 5

(5)

50000 cycles.

(6)

6

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