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BQ24721CRHBT Datasheet(PDF) 2 Page - Texas Instruments |
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BQ24721CRHBT Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 60 page  www.ti.com DEVICE INFORMATION bq24721, bq24721C SLUS683C – NOVEMBER 2005 – REVISED DECEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION BATTERY SHORTED THERMISTOR ORDERING NUMBER PART NO. PACKAGE (VERY LOW BATTERY QUANTITY SENSE (TAPE AND REEL) VOLTAGE) OPERATION bq24721RHBR 3000 32 PIN Charge Current Changes to bq24721 TS 5x5mm QFN C/8 bq24721RHBT 250 bq24721CRHBR 3000 32 PIN Charge Current Changes to bq24721C TS 5x5mm QFN C/8 bq24721CRHBT 250 PACKAGE THERMAL DATA TA ≤ 40°C DERATING FACTOR PACKAGE(1) θ JA POWER RATING ABOVE TA = 25°C RHB(2) 36 °C/W 2.36 W 0.028 W/ °C (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. (2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2 ×3 via matrix. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NO. NAME Charge enable logic level low input. Logic HI on the CHGEN pin disables the charger. Logic LO on the 1 CHGEN CHGEN pin enables the charger. When the SMBus control register = bit0, CHGEN is also LO. AC adapter to system switch driver output. Connect directly to the gate of the ACFET PMOS power FET. Connect the FET source to the PVCC node and negative side of the input current-sense resistor. Connect the FET drain to the system load side. Recommend placing a 10-k Ω resistor from the gate to 2 ACDRV the source of the Bypass FET. If needed, an optional capacitor from gate to source of the ACFET is used to help slow down the ON and OFF times. The internal gate drive is asymmetrical allowing a quick turn-off and slower turn-off in addition to the internal break-before-make logic with respect to the BATDRV. Adapter current sense resistor, negative input. An optional 0.1- µF ceramic capacitor is placed from this 3 ACN pin to AGND for common-mode filtering. An optional 0.1- µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. Adapter current sense resistor, positive input. Place this on the adapter side of the input current sense 4 ACP resistor. Recommend placing a 0.1- µF ceramic capacitor from ACP to AGND to provide common-mode filtering. AC adapter detected sense voltage input. Connect a voltage divider resistor from adapter input (before Bypass FET) to ACDET, and another resistor from ACDET to AGND, in order to program adapter 5 ACDET detect threshold of 1.2 V. ACDET threshold should be greater than maximum battery regulation voltage, and lower than the minimum adapter voltage. Gate drive for the adapter input BYPASS switch to prevent reverse discharge from the battery to the input. Connect this pin directly to the gate of the input bypass PMOS power FET. The source of the FET is connected to the adapter input voltage node. Recommend placing a 10-k Ω resistor from the 6 BYPASS gate to the source of the BYPASS FET. The drain of the FET is connected to the positive node of the input current-sense resistor. An optional capacitor can be placed from the gate to the source to slow-down the switching times. Adjusting the turn-on and turn-off times is typically not needed for this FET. Error amplifier output for compensation. Connect the feedback compensation components from EAO 7 EAO to EAI. Typically a capacitor in parallel with a series resistor and capacitor. See the compensation calculation procedures. This node is internally compared to the PWM saw-tooth oscillator. 2 Submit Documentation Feedback |
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