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BQ24031RHLT Datasheet(PDF) 4 Page - Texas Instruments |
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BQ24031RHLT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 38 page www.ti.com ELECTRICAL CHARACTERISTICS bq24030, bq24031, bq24032A bq24035, bq24038 SLUS618F – AUGUST 2004 – REVISED NOVEMBER 2006 over junction temperature range (0°C ≤ T J ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT BIAS CURRENTS ICC(SPLY) Active supply current, VCC VVCC > VVCC(min) 1 2 mA V(AC) < V(BAT), V(USB) < V(BAT), Sleep current (current into BAT ICC(SLP) 2.6 V ≤ V I(BAT)≤ VO(BAT-REG), 2 5 pin) Excludes load on OUT pin VI(AC) ≤ 6 V, Total current into AC pin ICC(AS-STDBY) AC standby current with chip disabled, Excludes all loads, 200 CE=LOW, after t(CE-HOLDOFF) delay Total current into USB pin with chip ICC(USB-STDBY) USB standby current disabled, Excludes all loads, CE=LOW, 200 µA after t(CE-HOLDOFF) delay Total current into BAT pin with AC and/or USB present and chip disabled; ICC(BAT-STDBY) BAT standby current Excludes all loads (OUT and LDO), 45 60 CE=LOW, after t(CE-HOLDOFF) delay, 0°C ≤ T J≤ 85°C (1) Charge DONE, AC or USB supplying the IIB(BAT) Charge done current, BAT 1 5 load HIGH AC CUTOFF MODE VI(AC) > 6.8 V, AC FET (Q1) turns off, USB FET (Q3) turns on if USB power VCUT-OFF Input ac cutoff voltage, bq24035 6.1 6.4 6.8 V present, otherwise BAT FET (Q2) turns on. LDO OUTPUT Active only if AC or USB is present, VO(LDO) Output regulation voltage 3.3 V VI(OUT)≥ VO(LDO) + (IO(LDO) × RDS(on)) Regulation accuracy(2) –5% 5% IO(LDO) Output current 20 mA RDS(on) On resistance OUT to LDO 50 Ω C(OUT)(3) Output capacitance 1 µF OUT PIN-VOLTAGE REGULATION bq24030/31 VI(AC)≥ 6 V+VDO 6.0 6.3 Output bq24032A VI(AC)≥ 4.4 V+VDO 4.4 4.5 VO(OUT-REG) regulation V voltage VBSEL = HIGH or VBSEL = LOW, bq24038 4.4 4.5 VI(AC) > 4.4 V+VDO OUT PIN – DPPM REGULATION V(DPPM-SET) DPPM set point(4) VDPPM-SET < VOUT 2.6 5 V I(DPPM-SET) DPPM current source AC or USB present 95 100 105 µA SF DPPM scale factor V(DPPM-REG)= V(DPPM-SET) × SF 1.139 1.150 1.162 (1) This includes the quiescent current for the integrated LDO. (2) In standby mode (CE low) the accuracy is ±10%. (3) LDO output capacitor not required but one with a value of 0.1 µF is recommended. (4) V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG). 4 Submit Documentation Feedback |
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