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BQ24721 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ24721 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 60 page  www.ti.com bq24721, bq24721C SLUS683C – NOVEMBER 2005 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) 8 Vdc ≤ V (VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMISTOR COMPARATORS, TS Cold temperature threshold, TS pin V(LTF) V(TS) rising 72.8 73.5 74.2 %VREF5 voltage V(LTFH) Hysteresis for LTF threshold V(TS) falling 0.5 1 1.5 %VREF5 Cutoff temperature threshold, TS pin V(TCO) V(TS) rising 28.7 29.3 29.9 %VREF5 voltage Hot temperature threshold, TS pin V(HTF) V(TS) rising/falling 33.7 34.4 35.1 %VREF5 voltage V(TSDET) Pack thermistor insertion detected VT(S) rising/falling 82.45 85 87.55 %VREF5 Deglitch time for temperature out of V(TS) rising above V(LTF), or V(TS) falling below V(TCO) , or V(TS) falling below V(HTF) 16 µs range detection Deglitch time for temperature in valid V(TS) falling below (V(LTF) - V(LTFH)), or V(TS) rising above V(TCO) , or V(TS) rising 8 ms range detection above V(HTF) Deglitch time for thermistor removal V(TS) rising above V(TSDET) 16 µs detection V(TS) > V(TSDET) (pack removed) Deglitch time for thermistor insertion V(TS) falling below V(TSDET) 1 s detection V(TS) < V(TSDET) (pack inserted) CHARGE OVERCURRENT COMPARATOR V(OLP) Overcurrent protection threshold V(SYNP-SYNN) rising 200 %I(REG_CHG) V(OLPH) Hysteresis V(SYNP-SYNN) falling 20 %I(REG_CHG) Deglitch time V(SYNP-SYNN) rising and falling 1 µs SYNCHRONOUS to NONSYNCHRONOUS CURRENT COMPARATOR (ISYNSET) V(SYNSET) ISYNSET pin set voltage 1 V V(SYNP-SYNN) falling, K(SYNSET) ISYNSET current set factor 500 V/A ISYN_NSYN= (V(SYNSET) × K(SYNSET))/(R(SYNSET) × R(SENSE_CHG)) V(SYN_HYS) V(SYNP-SYNN) hysteresis voltage, rising V(SYNP-SYNN) rising 1.5 mV Deglitch time, Synch to Non-Synch V(SYNP-SYNN) rising and falling 1 µs ADAPTER OVERCURRENT COMPARATOR (ACOC) V(ACP-ACN) ≥ V(ACOC) , where SMBus charge mode register (0×12), % of 110 130 155 b6 = 1 = ACOC_protection_enabled, b8 = 0, b7 = 0 I(REG_DPM) V(ACP-ACN) ≥ V(ACOC) , where SMBus charge mode register (0×12), % of 130 150 175 b6 = 1 = ACOC_protection_enabled, b8 = 0, b7 = 1 I(REG_DPM) ACOC Input over-current protection V(ACOC) sense resistor voltage threshold V(ACP-ACN) ≥ V(ACOC) , where SMBus charge mode register (0×12), % of 150 170 195 b6 = 1 = ACOC_protection_enabled, b8 = 1, b7 = 0 I(REG_DPM) V(ACP-ACN) ≥ V(ACOC) , where SMBus charge mode register (0×12), % of 170 190 215 b6 1 = ACOC_protection_enabled, b8 = 1, b7 = 1 I(REG_DPM) V(ACOCH) ACOC Hysteresis V(SRP-SRN) falling 7 %I(REG_CHG) ACOC deglitch time before ACDRV V(ACP-ACN) rising 16 µs turns-off ACOC delay time after V(ACP-ACN)≤V(ACOC) before ACDRV V(ACP-ACN) falling, V(ACP-ACN)≤V(ACOC) 8 ms turn-on SYSTEM STATUS COMPARATORS INPUT SPECIFICATIONS Common mode input range at pin: 0 5 V ACDET VICR Common mode input range at TS pin 0.5 VREF5 V Common mode input voltage range 0 VCC V at pins: BAT, SYS Input bias currents at pins: ACDET, I(bias) 0.2 µA TS, BATDEP, SYS BATTERY DEPLETED COMPARATOR (BATDEP) V(BATDEP) = 2.2 V + V(step)× batdep_dac_code, where batdep_dac_code = 0 - 7, and Vstep = 0.1V, SMBus Charge Mode register 0 ×12, bits b9, b10, b11 V(BATDEP) BAT depleted voltage range For programmed V(BATREG) = 9 V, then cell = 2 2.2 2.9 V/cell For programmed V(BATREG) = 12 V - 14.4 V, then cell = 3 For programmed V(BATREG) = 16 V - 19.2 V, then cell = 4 BAT depleted accuracy -2% 2% Battery depleted detection deglitch V(BAT) falling 1 s time Battery not depleted detection V(BAT) rising 1 s deglitch time 8 Submit Documentation Feedback |
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