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AZ6425 Datasheet(PDF) 6 Page - Texas Instruments |
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AZ6425 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 56 page  www.ti.com DIGITAL CHARACTERISTICS ADS6425 SLWS197 – MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25 °C, min and max values are across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Fin = 10 MHz 88 Fin = 50 MHz 70 81 THD Total harmonic distortion Fin = 100 MHz 84 dBc Fin = 170 MHz 73 Fin = 230 MHz 72 ENOB Effective number of bits Fin = 50 MHz 10.8 11.4 Bits F1= 46.09 MHz, F2 = 50.09 MHz 90 IMD Two-tone intermodulation distortion dBFS F1= 185.09 MHz, F2 = 190.09 MHz 82 Near channel, Frequency of interfering signal 92 = 10 MHz Cross-talk dBFS Far channel, Frequency of interfering signal 105 = 10 MHz The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, I O = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 10 µA Low-level input current 10 µA Input capacitance 4 pF DIGITAL OUTPUTS High-level output voltage 1375 mV Low-level output voltage 1025 mV |VOD| Output differential voltage 250 350 450 mV VOS Output offset voltage Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance inside the device, from either output to Output capacitance 2 pF ground (1) IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair 6 Submit Documentation Feedback |
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