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ISL6123IRZA Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6123IRZA Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 21 page  10 FN9005.8 February 5, 2007 Using the ISL612XSEQEVAL1 Platform The ISL612XSEQEVAL1 platform is the primary evaluation board for this family. The board has two complete, separate and electrically identical circuits. See Figure 15 for its schematic and photograph. Additionally, there is an ISL6125 specific eval platform, ISL6125EVAL1, due to its unique open drain outputs for ease of evaluation. See Figure 16 for its schematic and photograph. In the top right hand corner of the board is a SMD layout with a ISL6123 illustrating the full functionality and small implementation size for an application having the highest component count. The majority of the board is given over to a socket and discrete through-hole components circuit for ease of evaluation flexibility through IC variant swapping and modification of UVLO levels and sequencing order by passive component substitution. The board is shipped with the ISL6123 installed in both locations and with two each of the other released variant types loose packed. As this sequencer family has a common function pinout there are no major modifications to the board necessary to evaluate the other ICs. To the left, right and above the socket are four test point strips (TP1, TP2, TP3, TP4). These give access to the labeled IC I/O pins during evaluation. Remember that significant current or capacitive loading of particular I/O pins will affect functionality and performance. Attention to orientation and placement of variant ICs in the socket must be paid to prevent IC damage or faulty evaluation. The default configuration of the ISL612XSEQEVAL1 circuitries was built around the following design assumptions: 1. Using the ISL6123IR or ISL6124IR 2. The four supplies being sequenced are 5V (IN_A), 3.3V (IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels are ~80% of nominal voltages. Resistors chosen such that the total resistance of each divider is ~10k using standard value resistors to approximate 80% of nominal = 0.63V on UVLO input. Resistor choice is such that I x R2 = 0.633V at the desired UV (undervoltage) level as the monitored voltage decreases. Total resistance in the divider is a factor for the designer to consider for accuracy of UV level and efficiency vs electrical noise immunity trade-offs. 3. The desired order turn-on sequence is first both 5V and 3.3V supplies together and then the 2.5V supply about 75ms later and lastly the 1.5V supply about 45ms later. 4. The desired turn-off sequence is first both 1.5V and 3.3V supplies at the same time then the 2.5V supply about 50ms later and lastly the 5V supply about 72ms after that. All scope shots are taken from ISL612XSEQEVAL1 board. Figures 7 and 8 illustrate the desired turn-on and turn-off sequences respectively. The sequencing order and delay between voltages sequencing is set by external capacitance values, so other than illustrated can be accomplished. FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF Typical Performance Curves (Continued) 1 μs/DIV 5VOUT GATE SYSRST# 2V/DIV 3.3VOUT Vmonitored R1 R2 UVLO Vmon/0.633mV = R1+R2/R2 when Vmon = desired UV level as Vmon decreases. For example, a 5V supply with a desired UV level at 4V would mean R1+R2/R2 = 6.319. Ideally, any R1 and R2 combination that met this ratio would work, but with only standard value resistors available, small deviations will occur. ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 |
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