ISL6443IRZ datasheet(10/18 Pages) INTERSIL

Part #	ISL6443IRZ

Description	300kHz Dual, 180째 Out-of-Phase, Step- Down PWM and Single Linear Controller

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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10 / 18 page

10

FN9044.2

August 9, 2006

Pin Descriptions

BOOT2, BOOT1 - These pins power the upper MOSFET

drivers of each PWM converter. Connect this pin to the

junction of the bootstrap capacitor and the cathode of the

bootstrap diode. The anode of the bootstrap diode is

connected to the VCC_5V pin.

UGATE2, UGATE1 - These pins provide the gate drive for

the upper MOSFETs.

PHASE2, PHASE1 - These pins are connected to the junction

of the upper MOSFETs source, output filter inductor and lower

MOSFETs drain.

LGATE2, LGATE1 - These pins provide the gate drive for

the lower MOSFETs.

PGND - This pin provides the power ground connection for

the lower gate drivers for both PWM1 and PWM2. This pin

should be connected to the sources of the lower MOSFETs

and the (-) terminals of the external input capacitors.

FB3, FB2, FB1 - These pins are connected to the feedback

resistor divider and provide the voltage feedback signals for

the respective controller. They set the output voltage of the

converter. In addition, the PGOOD circuit uses these inputs

to monitor the output voltage status.

ISEN2, ISEN1 - These pins are used to monitor the voltage

drop across the lower MOSFET for current loop feedback

and overcurrent protection.

PGOOD - This is an open drain logic output used to indicate

the status of the output voltages. This pin is pulled low when

either of the two PWM outputs is not within 10% of the

respective nominal voltage, or if the linear controller output is

less than 75% of it’s nominal value.

Table 1 shows detailed status of PGOOD which can be

classified into 4 cases under different combinations of SD1

and SD2 inputs.

The first case is when both SD1 and SD2 are HIGH.

PGOOD will be HIGH if all FB pins from the 3 REQUIRED

outputs are within regulation AND soft-starts (SS1 AND SS2)

are complete.

The other two cases are when either of SD1 or SD2 is LOW

which means the system wants to shut down one of the

PWM outputs but still wants to keep another output working.

PGOOD will be HIGH if all the FB pins from the 2

REQUIRED outputs are within regulation AND soft-start

(SS1/SS2) is complete.

The last case is when both of the SD1 and SD2 are LOW.

PGOOD will be low.

SGND - (Pin 20 on the TSSOP; Pin 17 on the QFN)

This is the small-signal ground, common to all 3 controllers,

and must be routed separately from the high current ground

(PGND). All voltage levels are measured with respect to this

pin. Connect the additional SGND pins to this pin. If using a

5V supply, connect this pin to VCC_5V. A small ceramic

capacitor should be connected right next to this pin for noise

decoupling.

VIN - Use this pin to power the device with an external

supply voltage with a range of 5.6V to 24V. For 5V ±10%

operation, connect this pin to VCC_5V.

VCC_5V - This pin is the output of the internal 5V linear

regulator. This output supplies the bias for the IC, the low

side gate drivers, and the external boot circuitry for the high

side gate drivers. The IC may be powered directly from a

single 5V (±10%) supply at this pin. When used as a 5V

supply input, this pin must be externally connected to VIN.

The VCC_5V pin must be always decoupled to power

ground with a minimum of 4.7

µF ceramic capacitor, placed

very close to the pin.

SYNC - This pin may be used to synchronize two or more

ISL6443 controllers. This pin requires a 1K resistor to

ground if used; connect directly to VCC_5V if not used.

SS1, SS2 - These pins provide a soft-start function for their

respective PWM controllers. When the chip is enabled, the

regulated 5

µA pull-up current source charges the capacitor

connected from this pin to ground. The error amplifier

reference voltage ramps from 0 to 0.8V while the voltage on

the soft-start pin ramps from 0 to 0.8V.

SD1, SD2 - These pins provide an enable/disable function

for their respective PWM output. The output is enabled when

this pin is floating or pulled HIGH, and disabled when the pin

is pulled LOW.

GATE3 - This pin is the open drain output of the linear

regulator controller.

OCSET2, OCSET1 - A resistor from this pin to ground sets

the overcurrent threshold for the respective PWM.

TABLE 1.

SD1

SD2

LDO>75%?

90%<FB1<110%?

90%<FB2<110%?

SS1 COMPLETED? SS2 COMPLETED?

PGOOD

11

Y

1

10

Y

x

Y

x

1

01

Y

x

Y

x

Y

1

00

x

0

“x“ means “don’t care“.

ISL6443

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