2

FN8213.2

July 5, 2006

Block Diagram

WR3

DCP3

WR2

DCP2

WR1

DCP1

WR0

DCP0

POWER-UP,

INTERFACE,

CONTROL AND

StAtus LOGIC

NON-VOLATILE

REGISTERS

INTERFACE

SDA

SCL

A2

A1

A0

WP

GND

Pin Descriptions

TSSOP PIN

SYMBOL

DESCRIPTION

1

RH3

“High” terminal of DCP3

2

RL3

“Low” terminal of DCP3

3

RW3

“Wiper” terminal of DCP3

4

A2

Device address for the

5SCL

6

SDA

Serial data I/O for the

7

GND

Device ground pin

8

RW2

“Wiper” terminal of DCP2

9

RL2

“Low” terminal of DCP2

10

RH2

“High” terminal of DCP2

11

RW1

“Wiper” terminal of DCP1

12

RL1

“Low” terminal of DCP1

13

RH1

“High” terminal of DCP1

14

A0

Device address for the

15

A1

Device address for the

16

Power supply pin

17

WP

Hardware write protection pin. Active low. Prevents any “Write” operation of the

18

RH0

“High” terminal of DCP0

19

RL0

“Low” terminal of DCP0

20

RW0

“Wiper” terminal of DCP0

X95840