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X9418YS24Z-2.7 Datasheet(PDF) 5 Page - Intersil Corporation |
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X9418YS24Z-2.7 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 20 page  5 FN8194.3 October 12, 2006 Figure 2. Instruction Byte Format The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P0) select which one of the two potentiometers is to be affected by the instruction. Bit 1 is defined to be 0. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the wiper counter register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the wiper counter register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9418; either between the host and one of the Data Registers or directly between the host and the wiper counter register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9418 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Figure 3. Two-Byte Instruction Sequence I1 I2 I3 I0 R1 R0 0 P0 Wiper Counter Register Select Register Select Instructions S T A R T 0101 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 0 P0 A C K SCL SDA S T O P X9418 |
Similar Part No. - X9418YS24Z-2.7 |
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