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X9520B20I-A Datasheet(PDF) 2 Page - Intersil Corporation |
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X9520B20I-A Datasheet(HTML) 2 Page - Intersil Corporation |
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2 / 30 page  2 FN8206.1 January 3, 2006 Block Diagram Detailed Device Description The X9520 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, V1/Vcc power-on reset control, V1/Vcc low voltage reset control, two supplementary voltage monitors, and integrated EEPROM with Block Lock™ protection, in one package. These functions are suited to the control, support, and monitoring of various system parameters in Fiber Channel/Gigabit Ethernet fiber optic modules, such as in Gigabit Interface Converter (GBIC) applications. The combination of the X9520 fucntionality lowers system cost, increases reliability, and reduces board space requirements using Intersil’s unique XBGA™ packaging. Two high resolution DCPs allow for the “set-and-forget” adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolution DCP may be used for setting sundry system parameters such as maximum laser output power (for eye safety requirements). Applying voltage to VCC activates the Power-on Reset circuit which allows the V1RO output to go HIGH, until the supply the supply voltage stabilizes for a period of time (selectable via software). The V1RO output then goes LOW. The Low Voltage Reset circuitry allows the V1RO output to go HIGH when VCC falls below the minimum VCC trip point. V1RO remains HIGH until VCC returns to proper operating level. A Manual Reset (MR) input allows the user to externally trigger the V1RO output (HIGH). Two supplementary Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it’s associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port. An application of the V1RO output may be to drive the “ENABLE” input of a Laser Driver IC, with MR as a “TX_DISABLE” input. V2RO and V3RO may be used to monitor “TX_FAULT” and “RX_LOS” conditions respectively. Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. The memory portion of the device is a CMOS serial EEPROM array with Intersil’s Block Lock™ protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other system parameters. The EEPROM array is internally organized as x 8, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. The device features a 2-Wire interface and software protocol allowing operation on an I2C™ compatible serial bus. DATA REGISTER COMMAND DECODE & CONTROL LOGIC SDA SCL POWER-ON / LOW VOLTAGE CONSTAT REGISTER PROTECT LOGIC EEPROM THRESHOLD RESET LOGIC 4 GENERATION RESET V2 VTRIP V1/Vcc VTRIP V3 + - 2 3 1 2kbit V1RO RH2 RW2 RL2 MR 8 6 - BIT NONVOLATILE MEMORY RH0 RW0 RL0 WIPER REGISTER RH1 RW1 RL1 COUNTER V2RO WP V3RO 7 - BIT NONVOLATILE MEMOR Y NONVOLATILE MEMOR Y WIPER REGISTER COUNTER WIPER REGISTER COUNTER ARRAY 8 - BIT 2 VTRIP + - + - X9520 |
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