2

FN8190.3

October 12, 2006

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked

out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the pots and pot

registers are input on this pin. Data is latched by the

rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the

X9401.

Chip Select (CS)

When CS is HIGH, the X9401 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS LOW enables the X9401, placing it

in the active power mode. It should be noted that after

a power-up, a HIGH to LOW transition on CS is

required prior to the start of any operation.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select the

device. Once the part is selected and a serial sequence

is underway, HOLD may be used to pause the serial

communication with the controller without resetting the

serial sequence. To pause, HOLD must be brought LOW

while SCK is LOW. To resume communication, HOLD is

brought HIGH, again while SCK is LOW. If the pause

feature is not used, HOLD should be held HIGH at all

times.

The address inputs are used to set the least significant 2

bits of the 8-bit slave address. A match in the slave address

serial data stream must be made with the address

input in order to initiate communication with the

X9401. A maximum of 4 devices may occupy the SPI

serial bus.

Potentiometer Pins

terminal connections on either end of a mechanical poten-

tiometer.

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to

the Wiper Counter Registers.

Ordering Information

PART NUMBER

PART

MARKING

LIMITS

(V)

POTENTIOMETER

ORGANIZATION (k

Ω)

TEMP

RANGE (°C)

PACKAGE

PKG. DWG.

#

X9401WS24IZ (Note)

X9401WS ZI

5 ±10%

10

-40 to 85

24 Ld SOIC (300 mil) (Pb-free)

MDP0027

X9401WS24I-2.7*

X9401WS G

2.7 to 5.5

10

-40 to 85

24 Ld SOIC (300 mil)

M24.3

X9401WS24IZ-2.7* (Note)

X9401WS ZG

-40 to 85

24 Ld SOIC (300 mil) (Pb-free)

MDP0027

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9401