1

®

FN8170.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

All other trademarks mentioned are the property of their respective owners

X9260

Dual Supply/Low Power/256-Tap/SPI bus

Dual Digitally-Controlled (XDCP™)

Potentiometers

FEATURES

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/pot–0.4% Resolution

• SPI Serial Interface for Write, Read, and Transfer

Operations of the Potentiometer

•

Wiper Resistance, 100

Ω typical @ V+ = 5V,

V- = -5V

• 4 Nonvolatile Data Registers for Each

Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position

on Power-up.

• Standby Current <5µA Max

•

50k

Ω, 100kΩ Versions of End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per

Register

• 24 Ld SOIC

• Low Power CMOS

V+ = 2.7V to 5.5V

V- = -2.7V to -5.5V

• Pb-Free Plus Anneal Available (RoHS Compliant)

DESCRIPTION

The

X9260

integrates

2

digitally

controlled

potentiometer (XDCP) on a monolithic CMOS

integrated circuit.

The digitally controlled potentiometer is implemented

using 255 resistive elements in a series array.

Between each element are tap points connected to the

wiper terminal through switches. The position of the

wiper on the array is controlled by the user through the

SPI bus interface. Each potentiometer has associated

with it a volatile Wiper Counter Register (WCR) and a

four nononvolatile Data Registers that can be directly

written to and read by the user. The contents of the

WCR controls the position of the wiper on the resistor

array though the switches. Power-up recalls the

contents of the default Data Register (DR0) to the

WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Bus

Interface

and Control

SPI

Bus

Address

Data

Status

Write

Read

Transfer

50k

Ω or 100kΩ versions

Inc/Dec

Power-on Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0-DR3)

Interface

Control

V-

Data Sheet

August 29, 2006