X40420V14Z-B datasheet(9/25 Pages) INTERSIL

Part #	X40420V14Z-B

Description	Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

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Manufacturer	INTERSIL [Intersil Corporation]

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9

May 25, 2006

BP: Block Protect Bit (Nonvolatile)

The Block Protect Bits BP determines which blocks of

the array are write protected. A write to a protected

block of memory is ignored. The block protect bit will

prevent write operations to half the array segment.

PUP1, PUP0: Power-uppower-up Bits (Nonvolatile)

The Power-up bits, PUP1 and PUP0, determine the

tPURST time delay. The nominal power-up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits

The bits WD1 and WD0 control the period of the

Watchdog Timer. The options are shown below.

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and

trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceded by a start and ended with a stop).

– Write a 06H to the Control Register to set the

Register Write Enable Latch (RWEL) and the WEL

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation proceeded by a start

and ended with a stop).

– Write a one byte value to the Control Register that

has all the control bits set to the desired state. The

Control register can be represented as qxys 001r in

binary, where xy are the WD bits, and st are the BP

bits and qr are the power-up bits. This operation pro-

ceeded by a start and ended with a stop bit. Since

this is a nonvolatile write cycle it will take up to 10ms

to complete. The RWEL bit is reset by this cycle and

the sequence must be repeated to change the non-

volatile bits again. If bit 2 is set to ‘1’ in this third step

(qxys 011r) then the RWEL bit is set, but the WD1,

WD0, PUP1, PUP0, and BP bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and

returns a NACK.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

Note: 1. tPURST is set to 200ms as factory default.

2. Watchdog timer bits are shipped disabled.

Fault Detection Register (FDR)

The Fault Detection Register provides the user the

status of what causes the system reset active. The

Manual Reset Fail, Watchdog Timer Fail and Three

Low Voltage Fail bits are volatile

The FDR is accessed with a special preamble in the

slave byte (1011) and is located at address 0FFh. It

can only be modified by performing a byte write opera-

tion directly to the address of the register and only one

data byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the con-

trol register to access this fault detection register.

Protected Addresses

(Size)

Memory

Array Lock

0

None

1

100h – 1FFh (256 bytes)

Upper Half of

Memory Array

PUP1 PUP0

Power-on Reset Delay (tPURST)

0

50ms

0

1

200ms (default)

1

0

400ms

1

800ms

WD1

WD0

Watchdog Time Out Period

0

1.4 seconds

0

1

200 milliseconds

1

0

25 milliseconds

1

disabled (factory default)

7

6543

2

1

0

LV1F LV2F

0

WDF MRF

0

X40420, X40421

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