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X5001PZ-2.7 Datasheet(PDF) 4 Page - Intersil Corporation |
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X5001PZ-2.7 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 20 page 4 FN8125.1 May 30, 2006 PIN CONFIGURATION PIN DESCRIPTION Pin (SOIC/PDIP) Pin TSSOP Name Function 11 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch- dog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 22 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 36 VPE VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V). 47 VSS Ground 814 VCC Supply Voltage 7 13 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active un- til VCC rises above the minimum VCC sense level for 200ms. RESET goes active if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long- er than the selectable watchdog time out period. A falling edge of CS/WDI will reset the watchdog timer. RESET goes active on power-up at 1V and remains active for 200ms after the power supply stabilizes. 3-5,10-12 NC No internal connections 8 Ld SOIC/PDIP X5001 CS/WDI SO 1 2 3 4 RESET 8 7 6 5 VCC VSS SCK SI SCK SI VSS VCC CS/WDI SO 1 2 3 4 8 7 6 5 8 Ld TSSOP RESET VPE VPE X5001 X5001 |
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