8

FN7173.2

May 5, 2006

Description of Operation

A simplified block schematic is shown in Figure 1. The

following description is intended to provide the user with

sufficient information to understand the effects of the

external components and signal conditions on the outputs of

the integrated circuit.

nominally 0.1µF. The clamp circuit A1 will prevent the input

signal on pin 4 going more negative than 1.5V, the value of

part of the video waveform, will be clamped at 1.5V. The

capacitor during the remaining portion of the H line,

approximately 58µs for a 15.75kHz timebase. From I • t = C • V,

the video time-constant can be calculated. It is important to

note that the charge taken from the capacitor during video

must be replaced during the sync tip time, which is much

shorter, (ratio of x 12.5). The corresponding current to

restore the charge during sync will therefore be an order of

cause sync tip crushing. For this reason, the internal series

resistance has been minimized and external high resistance

values in series with the input coupling capacitor should be

avoided. The user can exercise some control over the value

of the input time constant by introducing an external pull-up

resistance from pin 4 to the 5V supply. The maximum

level. For a net discharge current greater than zero, the

resistance should be greater than 450k. This will have the

effect of increasing the time constant and reducing the

adjustment, as explained later.

FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL

EL4583