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EL1510CSZ Datasheet(PDF) 7 Page - Intersil Corporation |
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EL1510CSZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 10 page 7 FN7122.2 March 26, 2007 Applications Information Product Description The EL1510 is a dual operational amplifier designed for line driving in DMT ADSL solutions. It is a dual current mode feedback amplifier with low distortion while drawing moderately low supply current. It is built using Elantec's proprietary complimentary bipolar process and is offered in industry standard pin-outs. Due to the current feedback architecture, the EL1510 closed-loop 3dB bandwidth is dependent on the value of the feedback resistor. First the desired bandwidth is selected by choosing the feedback resistor, RF, and then the gain is set by picking the gain resistor, RG. The curves at the beginning of the Typical Performance Curves section show the effect of varying both RF and RG. The 3dB bandwidth is somewhat dependent on the power supply voltage. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible, below ¼”. The power supply pins must be well bypassed to reduce the risk of oscillation. A 1.0µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor is adequate for each supply pin. For good AC performance, parasitic capacitances should be kept to a minimum, especially at the inverting input. This implies keeping the ground plane away from this pin. Carbon resistors are acceptable, while use of wire-wound resistors should not be used because of their parasitic inductance. Similarly, capacitors should be low inductance for best performance. FIGURE 25. TRANSIMPEDANCE vs TEMPERATURE FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Typical Performance Curves (Continued) 3.5 0 2 3 1 0.5 1.5 2.5 DIE TEMPERATURE (°C) -50 100 150 -25 0 50 125 25 75 1.136W θ JA =1 10° C/W SO 8 1.8 1.6 1.4 0.8 0.6 0.2 0 0 25 50 75 100 150 AMBIENT TEMPERATURE (°C) 125 85 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.4 1 1.2 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - DFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 4.5 4 3 2 1 0.5 0 0 25 50 75 100 150 AMBIENT TEMPERATURE (°C) 125 85 θ JA =4 3°C/ W DF N8 2.907W 3.5 2.5 1.5 781mW θ JA = 160 °C /W SO 8 & DF N8 1.2 1 0.8 0.6 0.2 0 0 25 50 75 100 150 AMBIENT TEMPERATURE (°C) 125 85 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.4 EL1510 |
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