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ISL6423BEVEZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6423BEVEZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 16 page  11 FN6412.1 April 10, 2007 Byte Format Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB). Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 6). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.) The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6423B will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. Transmission Without Acknowledge Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. This approach, though, is less protected from error and decreases the noise immunity. ISL6423B Software Description Interface Protocol The interface protocol is comprised of the following, as shown below in Table 2: • A start condition (S) • A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I2C slave address for the ISL6423B is 0001 0XXX) • A sequence of data (1 byte + Acknowledge) • A stop condition (P) System Register Format • R, W = Read and Write bit • R = Read-only bit All bits reset to 0 at Power-On TABLE 6. CONTROL REGISTER (SR4) Transmitted Data (I2C bus WRITE mode) When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR2 thru SR4) of the ISL6423B via I2C bus. These will be written by the microprocessor as shown below. The spare bits of registers can be used for other functions. SDA SCL FIGURE 6. ACKNOWLEDGE ON THE I2C BUS 1 2 8 9 ACKNOWLEDGE FROM SLAVE MSB START TABLE 2. INTERFACE PROTOCOL S 0 00 10A1A0 R/W ACK Data (8 bits) ACK P TABLE 3. STATUS REGISTER (SR1) R, W R, W R, W RRRRR SR1H SR1M SR1L OTF CABF OUVF OLF BCF TABLE 4. TONE REGISTER (SR2) R, W R, W R, W R, W R, W R, W R, W R, W SR2H SR2M SR2L ENT MSEL TTH X X TABLE 5. COMMAND REGISTER (SR3) R, W R, W R, W R, W R, W R, W R, W R, W SR3H SR3M SR3L DCL VSPEN X ISELH ISELL R, W R, W R, W R, W R, W R, W R, W R, W SR4H SR4M SR4L EN VTOP VBOT |
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