10

FN6400.0

March 21, 2007

Two scenarios can cause the input voltage over shoot. The

first one is when the AC adapter is inserted live (hot

insertion) and the second one is when the current in the

power PFET of the ISL9209B has a step-down change.

Figure 25 shows an equivalent circuit for the ISL9209B

input. The cable between the AC/DC converter output and

the handheld system input has a parasitic inductor. The

parasitic resistor is the lumped sum of various components,

such as the cable, the adapter output capacitor ESR, the

connector contact resistance, and so on.

During the load current step-down transient, the energy

stored in the parasitic inductor is used to charge the input

off the power PFET slowly during the OCP, the battery OVP

event, and when the device is disabled via the EN pin.

Because of such design, the input over shoot during those

events is not significant. During an input OVP, however, the

PFET is turned in less than 1µs and can lead to significant

over shoot. Higher capacitance reduces this type of over

shoot.

The over shoot caused by a hot insertion is not very

dependent on the decoupling capacitance value, especially

when ceramic type capacitors are used for decoupling. In

theory, the over shoot can rise up to twice of the DC output

voltage of the AC adapter. The actual peak voltage is

dependent on the damping factor that is mainly determined

by the parasitic resistance (R in Figure 25).

In practice, the input decoupling capacitor is recommended

to use a 16V X5R dielectric ceramic capacitor with a value

between 0.1µF to 1µF.

The output of the ISL9209B and the input of the charging

circuit typically share one decoupling capacitor. The

selection of that capacitor is mainly determined by the

requirement of the charging circuit. When using the ISL6292

family chargers, a 1µF, 6.3V, X5R capacitor is

recommended.

Layout Recommendation

The ISL9209B uses a thermally enhanced DFN package.

The exposed pad under the package should be connected to

the ground plane electrically as well as thermally. A grid of

1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5

vias per row is recommended (refer to the ISL9200EVAL1

evaluation board layout). The vias should be about 0.3mm to

0.33mm in diameter. Use some copper on the component

layer if possible to further improve the thermal performance

but it is not mandatory.

Since the ISL9209B is a protection device, the layout should

also pay attention to the spacing between tracks. When the

distance between the edges of two tracks is less than

0.76mm, an FMEA (failure mechanism and effect analysis)

should be performed to ensure that a short between those

two tracks does not lead to the charger output exceeding the

“Lithium-Safe” region limits. Intersil will have the FMEA

document for the solution using the ISL9209B and the

ISL6292C chip set but the layout FMEA should be added as

part of the analysis.

FIGURE 25. EQUIVALENT CIRCUIT FOR THE ISL9209B INPUT

AC/DC

ISL9209

ADAPTER

CABLE

HANDHELD SYSTEM

C1

L

R

C2

ISL9209B